Therefore, the present creation is not really intended to be limited to the embodiments demonstrated herein but is to be accorded the widest scope according to the rules and novel options disclosed herein.

A number of procedures might be used to detect no matter if the quantity of modifying setup violations is significant. A method is always to XOR the state of every detection circuit While using the past point out with the circuit and to check the number of ‘1’s that has a threshold. Another way is to determine The actual detection circuit that corresponds Using the predicted frequency applying STA (static timing Assessment) or through a calibration phase.

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One more delay line section might have N hold off features that create the maximum delayed monotone sign 230-N. AND gates in the hold off lines may well Each and every Use a reset enter RST to reset the road between the delay components to established the hold off line to an Preliminary recognised state.

In other additional specific areas of the invention, Each and every from the plurality of delayed monotone signals 230 could be either a a single or perhaps a zero. The Consider circuit 240 might determine whether the number of kinds within the plurality of delayed monotone signals differs from a drinking water level amount by much more than a predetermined threshold.

An aspect of the existing invention could reside in a method for detecting voltage tampering. In the method, a plurality of resettable delay line segments are provided. Resettable hold off line segments amongst a resettable hold off line phase linked to a minimum amount hold off time and also a resettable delay line segment connected to a optimum delay time are each connected to discretely growing hold off periods.

23. A method for detecting voltage tampering, comprising: providing a plurality of resettable hold off line segments, wherein resettable delay line segments in between a resettable delay line section affiliated with a minimal hold off time and a resettable hold off line phase affiliated with a most hold off time are Each and every linked to discretely expanding delay times;

The h2o stage variety could be decided based upon delayed monotone signals from a number of past Consider time 310. The plurality of resettable delay line segments could comprise faucets along a hold off line. Alternatively, the plurality of resettable hold off line segments comprises parallel delay traces.

9. The equipment for detecting clock tampering as outlined in declare eight, more comprising: implies for resetting the implies for delaying the monotone signal throughout a reset time period, whereby the reset period of time is ahead of the clock Examine time frame.

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a plurality of resettable delay line segments that hold off the monotone signal to crank out a respective plurality of delayed monotone indicators Each and every getting both a a single or maybe a zero logic price, wherein resettable hold off line segments in between a resettable hold off line segment connected to a minimal hold off time plus a resettable hold off line segment related to a maximum hold off time are Each individual associated with discretely rising hold off occasions; and

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The present invention relates frequently to detecting tampering with the clock and/or offer voltage of the processor.